This invention is in the field of integrated circuits and their manufacture. Embodiments of this invention are more particularly directed to integrated resistor structures constructed by advanced metal-oxide-semiconductor (MOS) technologies.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. As is fundamental in the art, reduction in the size of physical feature sizes of structures realizing transistors and other solid-state devices enables greater integration of more circuit functions per unit “chip” area, or conversely, reduced consumption of chip area for a given circuit function. The capability of integrated circuits for a given cost has greatly increased as a result of this miniaturization trend.
Advances in semiconductor technology in recent years have enabled the shrinking of the minimum device feature size (e.g., the width of the gate electrode of a metal-oxide-semiconductor (MOS) transistor, which defines the transistor channel length) into the extreme sub-micron range. State of the art transistor channel lengths are now approaching the sub-20 nanometer regime, which is on the same order of magnitude as the source and drain depletion widths. This scaling of MOS transistor feature sizes into the deep submicron realm has necessitated the thinning of the MOS gate dielectric layer, if conventional gate dielectric layers (e.g., silicon dioxide) are used, to an extent that can be problematic from the standpoint of gate current leakage, manufacturing yield and reliability. In response to this limitation of conventional gate dielectric material, so-called “high-k” gate dielectrics, such as hafnium oxide (HfO2), have become popular. These dielectrics have higher dielectric constants than silicon dioxide and silicon nitride, permitting those films to be physically thicker than corresponding silicon dioxide films while remaining suitable for use in high performance MOS transistors. Gate electrodes of metals and metal compounds, such as titanium nitride, tantalum-silicon-nitride, tantalum carbide, and the like are now also popular in modern MOS technology, especially in combination with these high-k gate dielectrics. These metal gate electrodes eliminate the undesired polysilicon depletion effect, which is particularly noticeable at the extremely small feature sizes required of these technologies.
A popular technique for fabricating integrated circuits with high-k metal gate MOS transistors is referred to in the art as the “replacement gate” processes. In a general sense, replacement gate processes form polysilicon MOS transistors in the conventional manner, including the defining of polycrystalline silicon (“polysilicon”) gate electrodes overlying a gate dielectric film, and the formation of source and drain regions in a self-aligned manner relative to those polysilicon gate electrodes. According to the replacement gate approach, those “dummy” polysilicon gate electrodes and the underlying “dummy” gate dielectric film are removed after implant of the source and drain regions, followed by deposition of high-k gate dielectric material and metal gate material at the locations previously occupied by the polysilicon gate electrode and gate dielectric. Chemical-mechanical polishing (CMP) of the deposited metal gate material planarizes the top surface of the gate electrode with the surrounding interlevel dielectric structures. By way of further background, commonly owned U.S. Pat. No. 8,062,966, issued Nov. 22, 2011, entitled “Method for Integration of Replacement Gate in CMOS Flow”, and incorporated herein by this reference, describes a high-k metal gate structure and process, according to which CMOS integrated circuits are constructed using a replacement gate process.
Resistor structures are now commonly implemented in many modern ultra-large scale integrated circuits. Polysilicon is an attractive material for use in forming these integrated resistors, especially as compared with metal materials. Polysilicon structures can be formed with relatively high resistivity, which reduces the area required to implement large value resistors as compared with metal resistor structures, and thus also reduces the parasitic inductance of those structures. Because polysilicon structures are typically dielectrically isolated from the underlying silicon substrate, polysilicon resistors generally have much lower parasitic capacitance than diffused resistors.
As known in the art, many integrated circuits include metal silicide cladding of silicon elements such as polysilicon transistor gate electrodes, polysilicon interconnects, and diffused regions, to improve the conductivity of those structures. Conventionally, this metal silicide cladding is performed by deposition of a metal (e.g., cobalt, titanium, tungsten) over the silicon structures followed by a high-temperature anneal to react that metal with the underlying silicon. The unreacted metal is then etched from those locations at which it was not in contact with underlying silicon. But silicide-cladding of polysilicon resistors is generally undesirable because of the resulting reduction in resistivity of the resistor structure. It has also been observed that unclad polysilicon resistors exhibit significantly more linear behavior with temperature than do silicide-clad polysilicon resistors, facilitating temperature compensation in sensitive circuits such as voltage reference circuits and the like.
Accordingly, conventional integrated circuits that are constructed with silicide-clad polysilicon conductors will still include unclad polysilicon resistors. Differentiation between the silicide-clad and unclad structures is conventionally accomplished by depositing a “silicide-block” dielectric film over the polysilicon conductors, followed by a masked etch of the silicide block film to expose those polysilicon conductors that are to be silicide-clad, and to protect those that are not to be clad (i.e., the resistor structures) from the direct react silicidation. However, it is cumbersome to incorporate the formation of unsilicided polysilicon resistors in conventional replacement gate process flows for forming integrated circuits with high-k metal gate transistors.
FIGS. 1a through 1g illustrate a conventional replacement gate process in which a polysilicon resistor is also constructed, beginning with a partially fabricated portion of a high-k metal gate CMOS integrated circuit as shown in cross-section in FIG. 1a. The structure of FIG. 1a is shown at a surface location of p-type single-crystal silicon substrate 4. P-type substrate 4 may be a portion of a p-type “well” formed by masked ion implantation into the substrate, or may simply be a location of a p-type substrate itself, in either case constituting locations at which n-type MOS transistors will be formed. Isolation dielectric structure 5, in the form of a shallow trench isolation (STI) structure, is disposed at the surface of substrate 4 for isolating transistors from one another. “Dummy” gate dielectric layer 7, for example of silicon dioxide, is disposed over the surface of substrate 4, over which polysilicon layer 8 is in turn disposed; “dummy” gate electrodes and a polysilicon resistor will be formed from this polysilicon layer 8 according to this conventional approach. Hard mask layer 9, for example of silicon nitride, overlies polysilicon layer 8 in this structure.
At the stage of manufacture shown in FIG. 1b, polysilicon structures 8 overlying remnants of dummy gate dielectric 7 have been formed by a masked etch of hard mask layer 9, followed by etch of polysilicon layer 8 and dummy gate dielectric layer 7 at those locations from which hard mask layer 9 were removed. Those polysilicon structures 8 formed at locations of the surface of substrate 4, and the underlying dummy gate dielectric at those locations will serve as dummy structures, and will not become part of the finished integrated circuit. Polysilicon structure 8′ is disposed over the surface of shallow trench isolation structure 5, and will form a polysilicon resistor in this conventional approach. Ion implantation has been applied to this structure after the formation of polysilicon structures, resulting in n-type drain extension regions 11 that are self-aligned with polysilicon structures 8, 8′.
FIG. 1c illustrates the structure after the deposition of sidewall dielectric layer 13 overall, followed by ion implantation of n+ source/drain regions 10 in a self-aligned manner relative to polysilicon structures 8, 8′ and sidewall dielectric structures formed in layer 13 along the sides of polysilicon structures 8, 8′. At the stage of manufacture shown in FIG. 1c, interlevel dielectric layer 14, for example of silicon dioxide, has been deposited overall. The structure is then planarized, for example by CMP, to a sufficient depth that remaining portions of hard mask layer 9 are removed, resulting in the surface interlevel dielectric 14 being substantially coplanar with the surface of polysilicon structures 8, 8′, as shown in FIG. 1d. 
Also as shown in FIG. 1d, polysilicon resistor structure 8′ is protected by hard mask feature 15, formed of a layer of deposited silicon nitride or the like subjected to a masked etch. Dummy gate polysilicon structures 8 and the underlying dummy gate dielectric layer 7 are then removed by a blanket etch, resulting in the structure shown in FIG. 1e. Polysilicon resistor structure 8′ remains in place at this stage, protected by hard mask feature 15.
Following removal of dummy gate polysilicon structures 8 and dummy gate dielectric 7, high-k dielectric layer 17 is deposited overall (typically overlying a thin interface layer, not shown), followed by the deposition of metal gate layer 18 overall (typically overlying a barrier metal layer, not shown), resulting in the structure of FIG. 1f. High-k dielectric 17 is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) of HfO2 or other similar high-k dielectric materials known in the art. Metal gate layer 18 is a layer of a metal or conductive metal compound that by its composition or by doping has a work function suitable for serving as the gate for MOS transistors of the desired conductivity type and with the desired threshold voltage. This structure is then subjected to CMP to remove metal gate layer 18 except from within those locations within openings of interlevel dielectric 14 previously occupied by dummy gate structures 8, to form the gate electrodes of the transistors at these locations, as shown in FIG. 1g. Overlying dielectric material and one or more metal conductor layers are then deposited overall, with contact openings formed through the dielectric material to interconnect the transistor gate structures 18, polysilicon resistor 8, source/drain regions 10, and other structures as desired for the eventual circuit.
It is useful to form a metal silicide cladding at the surface of those locations of polysilicon resistor 8′ at which overlying metal conductors will make contact to ensure good ohmic contact, while leaving the remainder of polysilicon resistor 8′ unsilicided. However, silicidation of any part of the surface of polysilicon resistor 8′ at this stage of manufacture is difficult because the post-silicidation removal of unreacted metal degrades the conductivity of contacts to metal gate electrodes 18. Furthermore, incorporation of the polysilicon resistor structure in these conventional replacement gate processes necessitates two additional photomasks: one for masking ion implantation of the resistor structure (i.e., to attain the correct resistivity) and another for forming the hard mask feature protecting resistor structure 8′ from the dummy gate removal etch. It has been further observed that adequate protection of non-silicided polysilicon resistor structures is even more difficult in those replacement gate process flows in which CMP is used to planarize the metal gate material, causing significant variability in the resistance presented by the polysilicon resistors.